I. Field of the Disclosure
The technology of the disclosure relates generally to instruction pipelining in processors, and more particularly to selectively storing micro-operations corresponding to an instruction sequence in a buffer.
II. Background
Instruction pipelining is a processing technique whereby the throughput of computer instructions being executed by a processor may be increased. In this regard, the handling of each instruction is split into a series of steps as opposed to each instruction being processed sequentially and fully executed before processing a next instruction. These steps are executed in an instruction pipeline composed of multiple stages. There are several cycles between the time an instruction is fetched from memory until the time the instruction is actually executed as the instruction flows through various pipeline stages of the instruction pipeline.
Conventionally, an instruction pipeline decodes an instruction after the instruction is fetched in a previous step. An instruction may be decoded into a series of shorter operations known as micro-operations or micro-ops. If a processor accesses a particular pattern of instructions multiple times (e.g., in a loop), the instruction pipeline may perform the same fetch and decode steps each time the same pattern of instructions is accessed. In this manner, processors may employ dedicated storage configured to store the micro-ops generated as a result of decoding a pattern of instructions. If the processor is instructed to access a pattern of instructions from a given fetch address, the processor searches the dedicated storage for the micro-ops corresponding to the fetch address. If the micro-ops have been previously decoded and stored in the dedicated storage, the micro-ops can be supplied from the dedicated storage to the processor, thus avoiding the need to re-fetch and re-decode the pattern of instructions. Supplying previously stored micro-ops for instructions to be executed rather than newly fetching and decoding such instructions allows the fetch and decode circuits in the instruction pipeline to be temporarily disabled, thus reducing power consumption.
A micro-op cache may be employed to provide dedicated storage for storing micro-ops for previously decoded instructions described above. A micro-op cache is conventionally configured to store micro-ops corresponding to a range of instruction patterns, including complex instruction sequences such as complex instruction loops. However, the ability to store micro-ops corresponding to complex instruction sequences generally results in a micro-op cache design having relatively high area and power consumption. In this regard, alternative to a micro-op cache, a micro-op buffer can be employed for storing micro-ops for previously decoded instructions. A micro-op buffer is conventionally designed to consume less area and power as compared to a micro-op cache. However, a micro-op buffer is only able to store micro-ops corresponding to simple instruction sequences, such as simple instruction loops, and not micro-ops corresponding to complex instruction sequences.
Thus, it would be advantageous to store micro-ops corresponding to complex instruction sequences in dedicated storage while consuming less area and power than provided by a micro-op cache.